Design for Test (DFT)
Scan, ATPG, MBIST, and JTAG — comprehensive testability for high-volume manufacturing.
Overview
We architect and implement DFT solutions that minimize area overhead while maximizing fault coverage. Our team handles scan insertion, ATPG pattern generation, memory BIST integration, boundary scan, and compression — ensuring your chip is testable, manufacturable, and yield-ready at the foundry.
Key Capabilities
Scan Architecture & Insertion
Full-scan and partial-scan architectures. Scan compression (OPMISR+, broadcast scan) to reduce test time and tester memory.
ATPG & Fault Coverage
Automatic test pattern generation with stuck-at, transition, and path-delay fault models. Coverage analysis and gap closure.
Memory BIST (MBIST)
MBIST controller insertion for SRAM, ROM, and register files. March algorithm selection, repair analysis, and redundancy.
JTAG & IEEE 1500
IEEE 1149.1 boundary scan implementation. IEEE 1500 core test wrappers for hierarchical test access.
Our Process
- 1DFT architecture planning and review
- 2Scan insertion with compression
- 3ATPG generation and fault simulation
- 4MBIST insertion and verification
- 5Pattern simulation on gate-level netlist with SDF
Tools & Technologies
Deliverables
- DFT-inserted netlist
- Scan chain reports and DRC-clean logs
- ATPG patterns (STIL / WGL)
- Fault coverage report (>99%)
- MBIST verification reports
Case Study
Digital Block DFT Insertion
Performed scan insertion and ATPG for a mid-complexity digital block. Achieved 99%+ stuck-at fault coverage with compressed scan patterns. Integrated MBIST for embedded SRAM instances. Pattern simulation verified on gate-level netlist with SDF annotation.
Need dft expertise?
Let's discuss your project. We'll scope the engagement and get back with a proposal within 48 hours.