Engineering notes and technical perspectives.
Read our latest thoughts on semiconductor design, verification methodologies, and industry training.
Addressing Timing Closure Challenges in Advanced FinFET Nodes
As we scale down to 5nm and beyond, routing congestion and RC delays are becoming the dominant bottlenecks in achieving timing closure. Here is how our physical design teams approach it.
Transitioning from RTL Design to UVM Verification
For RTL designers looking to expand their skill set, mastering the Universal Verification Methodology (UVM) is the next logical step. Learn the fundamental mindset shift required.
Understanding MBIST and ATPG in Modern SOCs
Design for Testability (DFT) is no longer an afterthought. With modern SOCs containing billions of transistors, robust MBIST and ATPG strategies are critical for yield.
Clock Domain Crossing: Why Your CDC Is Probably Broken
CDC bugs are the most expensive bugs in silicon — they survive simulation, evade formal tools, and show up only in the lab. Here's how to get CDC right the first time.
FPGA vs ASIC: Choosing the Right Path for Your Design
The FPGA-vs-ASIC decision isn't just about NRE cost anymore. Power, performance, volume, and time-to-market all play critical roles. Here's a framework for making the call.
UVM Sequences: Patterns That Actually Work at Scale
Most UVM tutorials teach you to write a simple sequence. Real testbenches need layered, reusable sequences that scale across hundreds of tests. Here are patterns our verification team swears by.
Power Analysis at RTL: Catching Power Bugs Before Synthesis
Waiting until gate-level to estimate power is too late. By then, architectural decisions are locked. Here's how we catch power-hungry RTL early in the design cycle.