TRK-04Back-End
Physical Design & Static Timing Analysis
Transform synthesized netlists into tape-out-ready GDSII layouts.
10 Weeks Intermediate to Advanced
Overview
A hands-on track that takes you through the complete physical design flow — floorplanning, placement, clock tree synthesis, routing, and sign-off. Students work with real industrial netlists to close timing, power, and area targets, ending with a DRC/LVS-clean GDSII.
What You'll Learn
- Define floorplans, power grids, and placement blockages
- Build balanced clock trees with minimal skew and insertion delay
- Perform detailed routing and fix DRC violations
- Run STA and close setup/hold timing across all corners
- Deliver a DRC/LVS-clean GDSII as capstone
Prerequisites
- Understanding of CMOS transistor operation
- Basic knowledge of RTL-to-GDSII flow
- Familiarity with TCL scripting
Tools You'll Use
Synopsys ICC2 / Fusion CompilerCadence InnovusPrimeTime / Tempus for STACalibre / IC Validator for DRC/LVSStarRC / Quantus for extraction
Module-wise Curriculum
- Die size estimation and aspect ratio
- Macro placement and pin assignment
- Power grid design and IR drop analysis
- Placement blockages and keep-out regions
Ready to start learning?
Join the next cohort of Physical Design & Static Timing Analysis. Limited seats per batch to ensure quality mentorship.