TRK-01Front-End
RTL Design with Verilog & SystemVerilog
Master the art of describing digital hardware at the register-transfer level.
10 Weeks Beginner to Intermediate
Overview
A structured deep-dive into digital design fundamentals, Verilog HDL, and SystemVerilog for synthesis. Students design real hardware blocks — from simple FSMs to pipelined RISC-V cores — and validate them on FPGA. Every concept is reinforced through hands-on labs using industry-standard simulation and synthesis tools.
What You'll Learn
- Write synthesizable Verilog and SystemVerilog RTL for complex digital blocks
- Understand timing, pipelining, clock-domain crossing, and metastability
- Simulate and debug designs using waveforms and assertion-based checks
- Synthesize and implement designs on FPGA prototyping boards
- Build a complete pipelined processor core as a capstone project
Prerequisites
- Basic knowledge of digital logic (gates, flip-flops, FSMs)
- Familiarity with any programming language (C, Python, etc.)
- No prior HDL experience required
Tools You'll Use
Verilog / SystemVerilogModelSim / QuestaVivado / QuartusFPGA Boards (Xilinx / Intel)Git & Makefiles
Module-wise Curriculum
- Combinational & sequential logic review
- Finite State Machines — Mealy, Moore, state encoding
- Timing analysis: setup/hold, max frequency, metastability
- Clock domain crossing techniques
Ready to start learning?
Join the next cohort of RTL Design with Verilog & SystemVerilog. Limited seats per batch to ensure quality mentorship.