TRK-03DFT
Design for Test (DFT)
Ensure manufacturing quality through scan insertion, ATPG, and memory BIST.
8 Weeks Intermediate
Overview
Learn how to make complex SoCs testable. This track covers scan chain architecture, Automatic Test Pattern Generation (ATPG), Memory BIST, boundary scan (JTAG), and compression techniques. Students work on inserting DFT logic into real gate-level netlists and generating high-coverage test patterns.
What You'll Learn
- Insert scan chains and perform DFT DRC checks
- Generate ATPG patterns and analyze fault coverage
- Implement memory BIST controllers for SRAM/ROM instances
- Integrate IEEE 1149.1 (JTAG) and IEEE 1500 wrappers
- Close coverage to >99% on a production-style SoC block
Prerequisites
- Understanding of digital logic and flip-flop operation
- Basic knowledge of Verilog
- Familiarity with synthesis flow is helpful
Tools You'll Use
Synopsys DFT Compiler / TestMAXTessent (Mentor/Siemens)Tetramax ATPGVCS / Questa for simulationTCL scripting
Module-wise Curriculum
- Scan flip-flop types: muxed-D, LSSD, clocked-scan
- Scan chain insertion and stitching
- DFT DRC rules and violations
- Scan compression: broadcast, Illinois scan, OPMISR+
Ready to start learning?
Join the next cohort of Design for Test (DFT). Limited seats per batch to ensure quality mentorship.