TRK-02Verification
Functional Verification with UVM
Build scalable, reusable testbenches using industry-standard verification methodology.
12 Weeks Intermediate to Advanced
Overview
Move beyond directed testing into constrained-random, coverage-driven verification using SystemVerilog and UVM. This track covers the complete verification flow — test plan creation, UVM component architecture, scoreboards, functional coverage, and regression management on real IP-level designs.
What You'll Learn
- Architect modular UVM testbenches with agents, monitors, drivers, and scoreboards
- Write constrained-random stimulus and track functional coverage
- Debug failing tests using waveforms, logs, and UVM reports
- Implement register abstraction layer (RAL) for configuration
- Verify an AHB/AXI-based design end-to-end as capstone
Prerequisites
- Working knowledge of Verilog or SystemVerilog
- Understanding of basic bus protocols (APB, AHB, or AXI)
- No prior UVM experience required
Tools You'll Use
SystemVerilog / UVM 1.2Questa / VCS / XceliumVerdi / DVE waveform viewerCoverage analysis toolsPython for regression scripting
Module-wise Curriculum
- Classes, inheritance, polymorphism
- Randomization and constraints
- Functional coverage groups and cross-coverage
- Virtual interfaces and clocking blocks
Ready to start learning?
Join the next cohort of Functional Verification with UVM. Limited seats per batch to ensure quality mentorship.